Scribe Zone Wafer Level Packaging (S-WLP)

S-WLP© is a refreshing approach to adopt the via-middle integration methodology to package your devices at the wafer level. By fabricating low resistivity interconnect vias on the scribe zone, your active device area is undisturbed giving you unparalleled gains in yield and device performance.

S-WLP Construction

Advantages of S-WLP

- Interconnect vias as small as 5um in diameter with high aspect ratio of 10 can be fabricated.

- Interconnect vias are placed on the scribe zone and therefore there is no disturbance in the active device area during processing.

- Low resistivity interconnect vias are suitable for all semiconductor & MEMS devices.

- Short connection lines from peripheral contact pads to the vias minimizes power loss.

- Enables chip size packaging to reduce form factor of the packaged devices.

- Eliminates the use of 3D lithography processes and therefore offers minimal process risks.