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If you are looking for solutions to minimize your device dimensions or want to add more functions to your existing device size,
please call +65 6546 5756 or write to sales@connectingcircuits.com

 

 

News ::


April 2009: Intelligent Chip Connections awarded the Technology Innovation Grant by SPRING Singapore for development of WLIM© technology

 

Sep 2010: Intelligent Chip Connections successfully demonstrates fully functional CMOS device wafers developed using its patented WLIM© architecture

 

 

 
 
TSV - Hybrid Via Integration Technology

Wafer Level Integration Module (WLIM)

 

WLIM© is an entirely new approach to fabricate and package microelectronic and MEMS devices on pre-fabricated interconnect wafers. By using ICC WLIM© wafers and its back end processes, integrated device manufacturers can enjoy double benefits of both via-first and via-last integration methodologies.

 

WLIM Construction

Advantages of WLIM

 

- Allows for devices to be fabricated on wafers with pre-existing interconnects that completely eliminate the via fabrication complications.

- Provides shortest electrical connection from device to board for reduced noise levels.

- Eliminates the need for devices to have contact pads, making them smaller. This maximizes wafer real estate and increases productivity.

- Redistribution of electrical connections on the back side of the wafers is done by exposing the interconnect vias after bonding the device front side. This ensures total protection of devices and enhances fabrication yield significantly.

- Device wafers are easier to handle because the interconnects are not through-wafer and hence the wafers are not structurally compromised.

- Interconnects are made using polysilicon vias that do not pose thermal mismatch problems and hence offer reliable electrical and thermal connectivity.

- Polysilicon interconnects are compatible with all front end semiconductor processing steps unlike metallic interconnects.

- Interconnects offer a uniform low resistivity ensuring reliability and minimal power loss.

- 3D integration and stacking of wafers is possible without the need for 3D TSVs or interposers.

- Packaging at wafer level now becomes part of the fabrication process rather than a downstream isolated process. This approach significantly reduces packaging cost and production yield.

 


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